Process Integration of Interconnects

This chapter aims to introduce the reader to the challenges of on-die interconnect integration as the semiconductor industry continues to march down the scaling path, with leading companies exercising high-volume production at 45 nm and lower nodes as of 2010. Before we dive into the state-of-the-art technology nodes, a brief review of the progression of complexity and incorporation of novel materials into the on-die interconnect architecture during the last twenty years should prove beneficial.