研究论文
Power-aware sourse feedback single-ended 7T SRAM cell at nanoscale regime
Chandramauleshwar Roy, Aminul Islam
Birla Institute of Technology, Mesra
来源Microsystem Technologies
年份2017
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工程Low-power high-performance VLSI design
Advancements in Semiconductor Devices and Circuit Design · Semiconductor materials and devices
参考文献 13
A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell
被引 103Aminul Islam, Mohd. Hasan · Microelectronics Reliability · 2011
Variation resilient subthreshold SRAM cell design technique
被引 33Aminul Islam, Mohd. Hasan, Tughrul Arslan · International Journal of Electronics · 2012
Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell
被引 12Anis Féki, Bruno Allard, David Turgis · 2012
此处列出前 3 条
引用本文 17
Design of low power, variation tolerant single bitline 9T SRAM cell in 16-nm technology in subthreshold region
被引 34Chandramauleshwar Roy, Aminul Islam · Microelectronics Reliability · 2021
Design of differential TG based 8T SRAM cell for ultralow-power applications
被引 27Chandramauleshwar Roy, Aminul Islam · Microsystem Technologies · 2018
A Reliable and Temperature Variation Tolerant 7T SRAM Cell with Single Bitline Configuration for Low Voltage Application
被引 22Bhawna Rawat, Poornima Mittal · Circuits Systems and Signal Processing · 2022
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