研究论文
Dual etch processes of via and metal paste filling for through silicon via process
Yong-Hyun Ham, Dong‐Pyo Kim, Kun-Sik Park, Ye-Sul Jeong, Ho‐Jin Yun, Kyu‐Ha Baek, Kwang‐Ho Kwon, Ki-Jun Lee 等 9 位
Electronics and Telecommunications Research Institute Korea University Chungnam National University
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逐年被引趋势
320
314
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25
被引次数 · OpenAlex
3.03
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同类平均 = 1
同类平均 = 1
前 9%
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同领域 · 同年份 · 同类型
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学术脉络
学科主题
工程Semiconductor materials and devices
Nanowire Synthesis and Applications · 3D IC and TSV technologies
参考文献 18
Silicon etch process options for micro- and nanotechnology using inductively coupled plasmas
被引 53Colin Welch, Andy Goodyear, T. Wahlbrink · Microelectronic Engineering · 2006
Control of sidewall slope in silicon vias using SF6∕O2 plasma etching in a conventional reactive ion etching tool
被引 46R. F. Figueroa, S. Spiesshoefer, S. L. Burkett · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 2005
Direct patterning of silicon oxide on Si-substrate induced by femtosecond laser
被引 31Amirkianoosh Kiani, Krishnan Venkatakrishnan, Bo Tan · Optics Express · 2010
此处列出前 3 条
引用本文 25
Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV)
被引 242Wen-Wei Shen, Kuan‐Neng Chen · Nanoscale Research Letters · 2017
Application of Through Glass Via (TGV) Technology for Sensors Manufacturing and Packaging
被引 69Yu Chen, Shaocheng Wu, Yi Zhong · Sensors · 2023
Galvanostatic bottom-up filling of TSV-like trenches: Choline-based leveler containing two quaternary ammoniums
被引 61Myung Jun Kim, Youngran Seo, Hoe Chul Kim · Electrochimica Acta · 2015
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