Stability and degradation of Si–GaN monolithic heterogeneous integration platform based on p-GaN gate GaN HEMTs

In this Letter, a monolithic heterogeneous integration platform based on a p-GaN/AlGaN/GaN epilayer is demonstrated, where Si pMOSFETs and p-GaN gate GaN HEMTs are co-integrated on the same Si substrate using the transfer printing and bonding technology. The fabricated Si–GaN hybrid CMOS inverter consisting of a Si pMOSFET and a p-GaN gate GaN HEMT exhibits excellent symmetry in noise margins (NML and NMH) and rise/fall times. A high peak voltage gain of 38 V/V is achieved with an ultralow hysteresis of 0.01 V, and the switching threshold remains close to VDD/2 with a drift of less than 0.25 V at 150 °C, while both NML and NMH retain more than 49% and 30% of VDD, respectively. Moreover, the integrated p-GaN gate GaN HEMTs maintain exceptional stability after complex compatibility processing, including an ultralow VTH hysteresis of 0.02 V, excellent gate reliability (ΔVTH < 0.5 V under stress), a small VTH shift of <0.12 V at 150 °C, a breakdown voltage of 1.88 kV, and a well-suppressed dynamic RON degradation (<30% at 1200 V). These results demonstrate that the optimized SiN insertion bonding layer and post-annealing process play a key role in mitigating stress mismatch, suppressing parasitic channel effects, and reducing dynamic RON degradation, achieving the outstanding high-temperature stability, noise immunity, and balanced driving capability of the Si–GaN integrated platform, which are essential for reliable operation in harsh environments. It is demonstrated that the proposed platform offers superior stability for both signal processing and power switching under high-temperature and high-voltage conditions, representing a promising solution for monolithic heterogeneous integrated power-driver chips.