Characterizing the Charge Trapping across Crystalline and Amorphous Si/SiO₂/HfO₂ Stacks from First-Principle Calculations

Charge trapping across multiple interfaces is a universal, important process in semiconductor devices such as high-$\ensuremath{\kappa}$ MOSFETs and nonvolatile memory. However, a straightforward simulation framework for such complicated physical processes, and systematic studies of them, are lacking. The authors combine first-principles calculations and Marcus charge-transfer theory in an optimized simulation framework, and apply it to Si/SiO${}_{2}$/HfO${}_{2}$ gate stacks to characterize hole trapping in high-$\ensuremath{\kappa}$ gate transistors. This insight and framework could be helpful for studying charge trapping in other semiconductor devices as well.