The Development and Technological Comparison of Various Die Stacking and Integration Options with TSV Si Interposer

Through Silicon Via (TSV) was original proposed for the three-dimensional (3D) IC packaging and now is realized in the high band width DRAM (HBM) application. TSV is also utilized in a passive silicon interposer and the insertion of such interposer into a flip chip packaging created another packaging platform commonly known as 2.5DIC for high density multiple ICs integration. However, since the 1st product announcement of FPGAs in 2011, the GPU integration with HBM is the other product until recently. High cost of ownership has been named for the main cause of 2.5D IC's slow adoptions, and the lack of standard that resulted in many process options contributing to the high cost for not meeting economic scale by each single option. There are four known processes options, using the form of interposer, single die or wafer, and when the ICs are attached to the interposer, before or after the entire interposer are completed, as naming conventions. With four years of development history and experience on all the above four process integration options, this paper will discuss the in details of the technology merits, challenges and solutions of each options. Comparison will be made in terms of the reliability and sustainable high yielding of the finished packages that contained high value ICs that is an ultimate decision factor for the adoption of Si interposer platform. Furthermore, considering different products endure different thermal budgets and to minimize the thermal processes after dies are attached, it derived to the suggestion of the CoW_last as the choice of process of record (PoR). The extendibility of CoW_last to the new generation of the more economic TSV-less packaging platform that are under development, will also be illustrated.