Development of Non-TSV Interposer (NTI) for High Electrical Performance Package

Nowadays, 2.5D and 3D stacked die technologies are under prosperous development for the benefit of transistor scaling and performance. However, with the trend of higher electrical performance, lower power consumption and cost effective demand, Non-TSV interposer (NTI) is one of the ways to meet the requirement. This paper introduces and demonstrates the NTI process flow, which includes chip-on-wafer (CoW) stacking, mold encapsulation, silicon removal and chip module-on-substrate (CMoS) etc. We successfully solved the high wafer warpage issue and epoxy material out-gassing problem through material selection and process condition change. As a result, all processes were processed without any handling and quality issue. New NTI chip module's warpage variation between room temperature and reflow's peak temperature is less than 35 um, which dramatically reduces the stress during CMoS process.