Ultra-low ESL capacitor based on Silicon technology with substrate embedded platform

As system on chip (SOC) has evolved to integrate more functions in semiconductor integrated circuit (IC), the market needs more advanced wafer fabrication technology which can implement low power system. With this change, the voltage fluctuation problem of low power has been more and more critical so, the engineers had tried to find effective solution to resolve the power delivery issue. Chip capacitors had been placed onto surface of substrate firstly, and capacitors had been moved into substrate for embedding with some applications to reduce the distance between SOC die and capacitor, resulted in performance improvement of power. But, impedance reducing of voltage has been remaining issue as the operating frequency of IC has been increased dramatically. Several ceramic capacitors for reducing equivalent series inductance (ESL) have been developed to overcome such kinds of issue and also, thin film capacitor has been suggested as another novel approach. Deep trench silicon capacitor based on silicon wafer fabrication processing technology has been utilized as one of effective way for device performance improvement. The authors present power integrity (PI) and thermally enhanced a new Si-based capacitor promising low ESL, high density capacitance and low z-profile form-factor, which is implemented by employing the legacy fabrication process which had been used for high density capacitor cell in DRAM (dynamic random access memory). We had noticed that the proven technology in DRAM products could be one of the best solution to make extremely low ESL capacitor. One of the most critical factors to determine the product success of mobile device is to achieve the competitive form factor including package height. This ultra low ESL capacitor is also very effective solution to make ultra thin profile capacitor and competitive package height eventually without sacrificial of capacitance at all. Here, we provide the comparative study of ultra low ESL silicon capacitor and conventional ceramic capacitor with substrate embedded platform for mobile SOC products. Power Delivery Network analysis based on the various structure and design options will be provided. In terms of ESL of capacitor and Z of PDN, while the low ESL ceramic capacitor called by LICC has ESL larger than 60 pH, the presented Si-based capacitor has ESL smaller than 3pH, which eventually reduces the peak value in self-impedance of PDN by 50%. Thermal performance analysis is performed also with various scenarios of mobile applications. With the electrical and thermal performance simulation analysis, the impact of new technology presented in this work on voltage drop of SOC package will be demonstrated through performance measurement evaluation finally. Actual SOC product for premium smartphone with package on package (POP) format will be used for the evaluation.