Chiplet Package for Automotive and Edge Processors

A package concept and technology is demonstrated that addresses next generation Edge Artificial Intelligence (AI), Internet-Of-Things (IOT), Industrial and Automotive Networking microprocessor performance requirements with memory and passive device embedding, while realizing competitive overall system cost. The memory interface has been designed in such a way such that “near face-to-face” memory access to the processor core can be achieved, while still providing adequate power and ground routing to maintain power integrity. The same package structure that is used for memory access is also used to place decoupling capacitors directly below the processor cores to effectively reduce noise in the power supply while using a minimal capacitor quantity and value compared to solutions with the capacitors further away from the processor device. The memory and capacitor integration is achieved by using fan-out (FO) package technology with design rules and area only necessary to effectively incorporate these devices. Final connection to the PCB is accomplished through laminate substrate technology to realize competitive overall system cost while still addressing electrical and thermal performance requirements.