A fast and simple method to place sub-die under Chip-let architecture based on thermal simulation

The traditional system on chip (SoC) puts all functions on a single silicon. With the evolution of advanced manufacturing process, the more functions of Soc, the larger the size of silicon die. Besides, the number of transistors increases and the physical size of the transistors decreases, the quantum effect and the rapid rise of manufacturing costs are a series of problem. The industry has been looking for a solution to the problem of SoC, and one possible solution is to design a chip using chip-let architecture. The chip-let is to distribute large-size multi-core design onto tiny raw die, and then encapsulate multiple chip-let in the same package with high-density interconnection provided by advanced packaging technology to form a chip system. When Chip-let architecture system contains a lot of small die, despite the advantages of flexible design and cost savings in chip-let architecture, the serious thermal issue and reliability problems caused by the unreasonable distribution of small die. Therefore, this paper propose a simple and fast method to determine the number of chip-let sub-die and sub-die distribution. The thermal simulation of the chip-let system in advance can provide a key reference for circuit design and system packaging, and provide important reference information such as the thermal peak value and temperature gradient distribution of the circuit for the reliability of the chip. In this paper a three-dimensional(3D) physical model is established and thermal simulation is completed by using MATLAB and COMSOL software. Then, to select the material properties, boundary conditions and heat transfer model of chip-let system. Finally the temperature distribution and thermal behavior in chip-let architecture are analyzed under the 3D model. It is very convenient to analyze the overall heat distribution of the chip-let architecture system instead of actually producing the die. In this way, the performance and reliability of the chip-let system can fast and simple be solved due to the excessive number or unreasonable distribution of die under the chiplet architecture, which may lead to the increase of system heat or local temperature.