Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time
K. Saino, S. Horiba, Shiro Uchiyama, Y. Takaishi, Mitsuru Takenaka, Taro Uchida, Y. Takada, K. Koyama 等 10 位
NEC (Japan) University of California, Berkeley
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摘要与影响
In this paper we propose a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics. For main-mode bits, leakage current can be attributed to junction thermal-generation leakage current. For tail-mode bits, it is found for the first time that Gate-Induced Drain Leakage (GIDL) current has a dominant impact. The root cause is electric field enhancement caused by metal precipitates located at the gate-drain overlap region.
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工程Semiconductor materials and devices
Advancements in Semiconductor Devices and Circuit Design · Integrated Circuits and Semiconductor Failure Analysis
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