First Demonstration of Vertical Bit-Line 1T1C 3D DRAM Based-On Stacked Dual-Gate IGZO FETs with Excellent P/NBTS and High On-State Current

For the first time, we experimentally demonstrate one novel vertical bit-line 3D 1T1C DRAM cells based-on dualgate IGZO FETs by monolithic integration. Contrary to singlegate and gate-all-around counterparts, this IGZO dual-gate 3D DRAM cells not only exhibit enhanced immunity to crosstalk coupling from adjacent cells but also retain the advantages of a cost-effective fabrication process. By extensive optimization of fabrication process, the fabricated multi-layer IGZO devices achieve high on-state current of$13 \mu \mathrm{A} / \mu \mathrm{m}{@}V_{\text{ov }}=V_{\text{ds }}=1 \mathrm{V}$and low SS of$73 \text{mV} / \text{dec}$among all the reported 3D 1T1C DRAM devices. Especially, high-temperature stability measurement of 3D DRAM devices is firstly evaluated at 85° C with minimum Vth shift of$\mathbf{5 5 m V}$in PBTS and$\mathbf{2 4 m V}$in NBTS. The threshold voltage of the devices is fine-tuned by top gate and bottom gate with large body factor for further lower leakage current. This work shows great prospect for high-density, low cost and highreliable IGZO 3D DRAM applications.