Investigation of Saturated Drain Current Change Phases For PMOS HCI Stressed at Ibmax
Wei-Cheng Chu, Bo-An Tsai, Yiheng Chen, Kun-Ham Hsieh
Powerchip (Taiwan)
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During the HCI Ibmax stress, PMOS's Idsat increased first and then decreased, it's different when stressed at Vg=Vd. From relevant information [1], we suspected that electrons injection and holes tunneling affected the phenomena. To explore the physical mechanisms, we studied different stress Vd, different channel length elements, and forward/reverse measurements. We concluded that Idsat increase the most under a short channel length element, larger stress Vd and forward measurement situation because of the different ΔVinter-dand ΔVinter-s; this affected the probability of electrons injection into the oxide near the drain side, and holes tunneling into oxide near the source side.
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工程Semiconductor materials and devices
Integrated Circuits and Semiconductor Failure Analysis · Advancements in Semiconductor Devices and Circuit Design
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