A High Bandwidth Capacitorless NMOS LDO with Pole-Tracking Scheme and Adaptive FFRC Achieving -65dB PSR across Full Load Range

This article presents a capacitorless linear low dropout regulator (LDO) with an N-type pass transistor that features high efficiency, fast transient and good power supply rejection (PSR) suitable for system-on-chip (SoC) integration. This LDO utilizes a pole-tracking compensation scheme and a transconductance-boosted (gm-boosted) folded-cascode EA to achieve high bandwidth. As a result, the LDO achieves a fast transient response and high PSR corner-frequency. Moreover, feedforward ripple cancellation (FFRC) is also incorporated to enhance the PSR performance further. The proposed LDO is fabricated in a 65nm CMOS process. It features PSR performance better than -65dB across the full load range at frequencies lower than 100kHz. And its undershoot and overshoot in response to a 1mA-to-100mA load transient with an edge time of 100ns are 83mV and 10mV, respectively.