Concurrent Dual Band CMOS LNA with improved IIP3 using Modified DS technique

For concurrent Dual-band low noise amplifiers (DB-LNA), this work provides a technique of linearization which enhances input third-order intercept point (IIP3) along with an improved output matching network, designed using a 65 nm CMOS technology for wireless and Bluetooth applications. For the linearization of dual-band LNAs, modified derivative superposition (DS) technique is described which suggests biasing the primary transistors in weak inversion (WI), while the transistor of auxiliary path in strong inversion (SI) zone. At 2.4 and 5.2 GHz, the LNA has input voltage reflection coefficient (S11) of -22.4 and -26.4 dB, respectively, and power gains (S21) of 14.24 and 11dB, noise figures of 2.4 and 4.4 dB, respectively, with input third-order intercept points (IIP3) of -1.66 and 0.04 dBm. From a 1 V supply, the LNA consumes DC power of 2.6mW.