研究论文

A low-power low-jitter adaptive-bandwidth PLL and clock buffer

Mozhgan Mansuri, Chih-Kong Ken Yang

University of California System

年份2003

DOI10.1109/isscc.2003.1234370

原文https://doi.org/10.1109/isscc.2003.1234370

阅读操作

确认中

在文库中上传 PDF 后可生成中文音频讲解。

摘要与影响

摘要 · 完整

A multi-context programmable on-chip communication network is implemented using a matrix of Flash-EEPROM pass-transistor switches (FPT) in a 0.18/spl mu/m technology. The prototype 8-context, 8/spl times/8 64b crossbar includes 576k FPT and >8k bi-directional tristate repeaters in an area of 1.38mm/sup 2/. Based on 2/spl times/2 building blocks, wave pipelining and elastic interconnect, data is transferred at 6.4Gb/s per channel, with independent clocks at both ends.

逐年被引趋势

320

313

关键指标

被引次数 · OpenAlex

4.25

领域内被引倍数
同类平均 = 1

前 5%

引用位次
同领域 · 同年份 · 同类型

参考文献

Google Scholar 与 OpenAlex 的被引统计范围不同，数值存在差异属正常。

AI 辅助阅读

依据：摘要

论文问答

当前基于摘要回答

可就本文提问；依据不足时会说明。

学术脉络

学科主题

工程

Advancements in PLL and VCO Technologies

Interconnection Networks and Systems · Analog and Mixed-Signal Circuit Design

参考文献 7

A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability

P. Larsson · IEEE Journal of Solid-State Circuits · 1999

被引 121

A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

K.-Y.K. Chang, Jason Wei, S. Li · 2003

被引 21

Embedded power supply for low-power DSP

Vadim Gutnik, Anantha P. Chandrakasan · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1997

被引 261

此处列出前 3 条

引用本文 23

A 27-mW 3.6-Gb/s I/O Transceiver

K.-L.J. Wong, Hamid Hatamkhani, Mozhgan Mansuri · IEEE Journal of Solid-State Circuits · 2004

被引 120

A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation

Seungkee Min, Tino Copani, Sayfe Kiaei · IEEE Journal of Solid-State Circuits · 2013

被引 96

A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration

Amr Elshazly, Rajesh Inti, Wenjing Yin · 2011

被引 27

按被引量排序，此处列出前 3 条

摘要与影响

摘要 · 完整

逐年被引趋势

320

313

关键指标

被引次数 · OpenAlex

4.25

领域内被引倍数
同类平均 = 1

前 5%

引用位次
同领域 · 同年份 · 同类型

参考文献

Google Scholar 与 OpenAlex 的被引统计范围不同，数值存在差异属正常。

学术脉络

学科主题

工程

Advancements in PLL and VCO Technologies

Interconnection Networks and Systems · Analog and Mixed-Signal Circuit Design

参考文献 7

A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability

P. Larsson · IEEE Journal of Solid-State Circuits · 1999

被引 121

A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

K.-Y.K. Chang, Jason Wei, S. Li · 2003

被引 21

Embedded power supply for low-power DSP

Vadim Gutnik, Anantha P. Chandrakasan · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1997

被引 261

此处列出前 3 条