15.6 A 36GB 3.3TB/S HBM4 DRAM with Per-Channel TSV RDQS Auto Calibration and Fully-Programmable MBIST
Sunghwan Joo, Jinyeon Kim, Yongsun Lee, Ji-Young Kim, Youngsik Lee, Yongmin Kim, Chisung Oh, Kyu-Ha Shim 等 25 位
Samsung (South Korea)
阅读操作
确认中在文库中上传 PDF 后可生成中文音频讲解。
摘要与影响
LLM-based generative AI requires high-capacity and high-bandwidth memory. We propose an HBM4 with 2048 I/Os, 3.3TB/s bandwidth, and 36GB cube density. Core die uses the 6thgen. DRAM and the base die uses a 4nm Fin-FET process. TSV count and data window are doubled for high-frequency margin. tCCDRis improved via per-channel TSV-RDQS auto calibration, enhancing rank-to-rank access. PMBIST enables at-speed testing in CoW and SiP. The on-die WDQS skew cancellation ensures robust timing, enabling reliable highspeed operation and improved yield.
逐年被引趋势
关键指标
同类平均 = 1
同领域 · 同年份 · 同类型
Google Scholar 与 OpenAlex 的被引统计范围不同,数值存在差异属正常。
AI 辅助阅读
依据:摘要
可就本文提问;依据不足时会说明。
学术脉络
学科主题
工程Low-power high-performance VLSI design
Advancements in PLL and VCO Technologies · 3D IC and TSV technologies
参考文献 3
此处列出前 3 条
引用本文 3
按被引量排序,此处列出前 3 条