Design and application of the high-voltage ultra-shallow junction PJFET

In this paper, the high-voltage, ultra-shallow junction PJFET was fabricated with the Bi-FET (JFET compatible bipolar) process. The device with the top-gate junction depth about 0.1 μm, the breakdown voltage more than 80 V, the gate-leakage current less than 5 pA, and the pinch-off voltage 0.8 V~2.0 V adjustable was realized. The PJFET and its Bi-FET process technology were used to design and process a high-precision integrated OPA. The measured results showed that the OPA has the bias current of less than 50 pA, the voltage noise of less than 50 nV/Hz1/2, and the current noise of less than 0.05 pA/Hz1/2.