Unveiling Time-Dependent Dynamics in MFMIS FeFETs

Metal–ferroelectric–metal–insulator–semiconductor (MFMIS) ferroelectric field-effect transistors (FeFETs) using an amorphous indium–tin–zinc-oxide (a-ITZO) channel and Hf0.5Zr0.5O2(HZO) ferroelectric layer are fabricated. By engineering the area ratio (AR = AI/AF) between the MIS transistor region and the MFM ferroelectric-capacitor region, the memory window (MW) can be continuously tuned while maintaining robust erase operation. To probe time-dependent behavior, single-sweep readouts are performed after program/erase pulses with a controlled delay time (Tdelay). We found that, as Tdelayincreases, the threshold voltage (Vth) shift of the program becomes larger than that of the erase under pulsed conditions, producing a progressive reduction—and at low AR, a possible inversion—of the MW. This asymmetric delay dependence has not been reported previously for oxide-semiconductor MFMIS FeFETs. Guided by the experimental trends, we propose a band-diagram-based mechanism that explicitly incorporates oxygen-vacancy-related traps at the HZO/floating-gate interfaces. The model attributes the observed evolution to the interplay among ferroelectric polarization relaxation, charge trapping/de-trapping in the floating gate. These findings establish AR engineering and delay-aware operation as effective levers to optimize MW, retention, and erase behavior in AOS-based MFMIS FeFETs, paving the way for compensation-free display drivers and embedded non-volatile memory.