A CMOS smart temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.1/spl deg/C from -55/spl deg/C to 125/spl deg/C

A smart temperature sensor in 0.7 /spl mu/m CMOS is accurate to within /spl plusmn/0.1/spl deg/C (3/spl sigma/) over the full military temperature range of -55/spl deg/C to 125/spl deg/C. The sensor uses substrate PNP transistors to measure temperature. Errors resulting from nonidealities in the readout circuitry are reduced to the 0.01/spl deg/C level. This is achieved by using dynamic element matching, a chopped current-gain independent PTAT bias circuit, and a low-offset second-order sigma-delta ADC that combines chopping and correlated double sampling. Spread of the base-emitter voltage characteristics of the substrate PNP transistors is compensated by trimming, based on a calibration at one temperature. A high trimming resolution is obtained by using a sigma-delta current DAC to fine-tune the bias current of the bipolar transistors.