State-of-the-Art Power Electronics in AI Data Centers

The rapid scaling of artificial intelligence (AI) workloads is driving a fundamental redesign of the data center power-delivery chain, from the utility grid to the processor die. This review paper presents a stage-by-stage technical benchmarking of state-of-the-art power electronics across the four key conversion stages that define this chain: the power supply unit (PSU), the high-voltage intermediate bus converter (HV IBC), the on-board low-voltage intermediate bus converter (LV IBC) and voltage regulator module (VRM), and the wide-bandgap (WBG) semiconductor devices that enable each stage. For the conventional AC-distributed architecture, totem-pole power factor correction (PFC) and LLC resonant converter topologies are benchmarked across the 3–12 kW power range. The analysis identifies the component-scaling limitations that constrain PSU power density and motivate the transition toward high-voltage direct-current (HVDC) distribution. For the emerging 800 V HVDC architecture, input-series-output-parallel (ISOP)-based GaN LLC converters are shown to achieve power densities exceeding 20 times those of conventional PSUs while maintaining comparable efficiency. In addition, fault-protection challenges unique to DC distribution are systematically analyzed. At the board level, LV IBC, VRM, and direct 48 V-to-point-of-load (PoL) conversion architectures are comparatively evaluated in terms of efficiency, power density, transient response, and thermal performance. This evaluation establishes a topology-to-performance mapping and provides a structured comparison between conventional two-stage and emerging single-stage power-delivery architectures. At the device level, commercial 1200 V SiC MOSFETs are benchmarked against 650 V GaN HEMTs for HVDC applications, while low-voltage Si MOSFETs are compared with 15–100 V GaN HEMTs for board-level conversion stages. Key figures of merit, including Ron×Qg, package area, current density, and cost per ampere, are used to quantify where wide-bandgap technologies have surpassed silicon and where challenges related to cost, current capability, and packaging maturity continue to limit adoption. By consolidating circuit-level and device-level benchmarks within a unified grid-to-chip framework, this review identifies the dominant efficiency–power density–voltage–cost tradeoffs across each conversion stage and provides insights into the development of a scalable, high-density power-delivery ecosystem for next-generation AI server racks .