Improving Read Performance for LDPC-Based SSDs with Adaptive Bit Labeling on $V_{th}$ States

NAND-based Solid-State Disks (SSDs) have become the mainstream storage solution thanks to their high I/O performance and data persistency. Modern SSDs boost their storage capacity by increasing the flash cell-bit density, resulting in severe leakage-induced bit errors over time. Low-Density Parity-Check (LDPC) is a common error correcting code for flash memory, which features incremental decoding strength levels through adding extra voltage sensing levels. However, when bit error rate becomes high, LDPC decoding with strong correction will be very slow. In this study, we identify that the read latency is strongly correlated with the method of bit labeling on cell threshold-voltage states, and based on this finding we propose using adaptive bit labeling to optimize the SSD read latency. Specifically, our method employ 2-3-2 Gray Coding as the default mode, and frequently-read data will be switched to using the least-significant page and center-significant page with 1-2-4 Gray Coding for fast reading. Our experimental results show that our design greatly outperforms static bit labeling and a state-of-the-art method.