Metal-Assisted Chemical Etching Toward Scallop-Free-Sidewall Through-Silicon Vias: A Review

With recent advancement and progress in the field of 3-D integration for modern high-speed and high-bandwidth electronic systems, there is an ever-increasing demand for high-quality through-silicon via (TSV) as a vertical interconnect. Some existing TSV fabrication processes, such as deep reactive ion etching (DRIE), show fabrication complexity and require major capital investment for equipment and maintenance. More importantly, the DRIE process leaves scallops on the via sidewall as the result of the fabrication process requiring cyclic etching and coating multiple times. This sidewall roughness negatively impacts on high-frequency interconnects, where the surface roughness significantly contributes to the conductor loss associated with the elongated current pathway and scattering at the interface of the substrate and the conductor. Meantime, metal-assisted chemical etching (MACE) has attracted enormous interest in recent years due to its fabrication simplicity and cost-effectiveness in the fabrication process and maintenance. Moreover, it offers a supersmooth sidewall (approximately tens of nanometers) and has huge potential for high-performance TSV fabrication. In this article, a comprehensive review on current TSV fabrication technologies and recent progress in the MACE-based fabrication process is reported where prior work on the MACE-based process is compared in terms of the catalyst type, etch rate, feature size, and sidewall roughness.