Gaussian Process Regression–Driven Thermal Modeling of 5 nm Stacked Nanosheet FETs for Advanced CMOS Thermal Management and Reliability

The reliability of sub-5 nm nanosheet FETs (NS-FETs) is severely constrained by self-heating effects, which lead to elevated channel temperatures, performance degradation, and reduced device lifetime due to BTI, HCI, and TDDB effects. To address these challenges, this work presents an integrated thermally aware TCAD–ML–MOBO optimization framework for 5 nm NSFET device design. A comprehensive electrothermal TCAD dataset is generated by systematically varying geometric and bias parameters to extract thermal resistance (Rth) and temperature rise (ΔT). A customized Gaussian Process Regression (GPR) surrogate model is proposed for efficient thermal prediction, achieving anR2score of 0.99 forRthwith low predictive uncertainty. This surrogate model is further integrated with a Multi-Objective Bayesian Optimization (MOBO) framework using the q-NEHVI acquisition strategy to simultaneously minimizeRthand ΔT. The optimized structure reduces temperature while maintaining electrical feasibility, with stable convergence evidenced by increasing hypervolume over 50 iterations. The resulting Pareto frontier demonstrates key trade-offs between NSFET geometric parameters for improved electrothermal performance. The proposed integrated framework demonstrates scalable, data-driven thermal optimization aligned with IRDS reliability targets for applications in advanced CMOS thermal management and enhanced reliability.