A 1.2 V Single Event Multinode Upset Tolerant RHSC 12T Memory Cell in 65-nm CMOS

This article introduces the RHSC-12T memory cell, specifically designed for neuromorphic applications to withstand soft errors caused by energy particles during technology scaling. Featuring 12 transistors and quad data storage nodes (reduced to three sensitive nodes), the memory cell minimizes susceptible areas by transferring the weakly driven node from the primary to the secondary storage node (${Q}$to${S}$), reducing the risk of single event upsets (SEUs). The proposed design ensures full tolerance to soft errors at any sensitive node and effectively mitigates single event multinode upsets (SEMNUs). Simulated using a 65 nm CMOS process at 1.2 V, the RHSC-12T exhibits write and read access times of 83.72 and 113.19 ps, respectively. Moreover, it demonstrates low power consumption, with leakage power at 1.25 nW, and occupies an area of$8.04~{\mu \text { m}}^{{2}}$.