Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes

The operation of static random access memory (SRAM) in the subthreshold region reduces both leakage power and access energy. Subthreshold operation is one of the proficient techniques to accomplish low-power and high performance system on chip. But the challenge, in subthreshold SRAM design, is the SRAM stability. The sensitivity to process variations increases with technology scaling resulting in reduced stability. In this paper, SRAM write stability is analyzed in the subthreshold region. The semi-analytical model of write static noise margin (WSNM) for 6T SRAM (subthreshold region) has been given in this paper. The results obtained from the analytical model are verified through simulations in Cadence using GPDK 45-nm, UMC 65-nm, and UMC 130-nm technology files. The model is based on the subthreshold current equations of the transistor. Further, the write stability of the SRAM is analyzed with the varying supply voltage and the sizing ratios. The process corner analyses is also accomplished to verify the write stability of the SRAM cell using the model at the worst process corners. To the best of the author's knowledge, this is the first model to analyze the WSNM based on the traditional butterfly static noise margin approach. It has been observed that the model is valid for all of the technology nodes, i.e., at 45 nm, 65 nm, as well as 130 nm. Also the model holds well for 8T and 10T SRAM configurations in addition to 6T SRAM cell.