Leakage Current in DRAM Memory Cell

Retention time is a critical characteristic in dynamic random access memory (DRAM) design. In order to improve DRAM retention time characteristics, leakage current must be reduced and various solutions are proposed. The major leakage paths in a DRAM cell stem from reverse junction leakage from the storage node, and gate induced drain leakage (GIDL) current. Empirically it is known that the junction leakage is affected by the lateral electric field near the storage node, which is enhanced by an increase in substrate doping due to threshold adjustment. The DRAM cell becomes more susceptible to GIDL when the storage node stores a "1" and a negative bias is applied to the gate. The voltage drop across the gate oxide creates a vertical electric field that leads to a higher leakage current. In this paper, these leakage paths are investigated with device simulation. Tradeoffs between substrate doping, gate thickness and leakage are explored using Silvaco Atonable/Atlas. The DRAM cell was modeled using a 0.24 mum NMOS transistor. Substrate doping was varied to analyze its effect on depletion region, lateral electric field, and reverse current. Device simulation has shown that a lower substrate doping yields better results on lateral field and reverse current. As the substrate doping was reduced from 5.8times1017cm-3to 9times1016cm-3, the lateral field decreased from 7.25times105V/cm to 5.6times105V/cm. Subsequently, the reverse current decreased from 3.1 pA to 0.5 pA. The GIDL was explored by varying LDD implantation energy and gate oxide thickness. As oxide thickness increased, the vertical field decreased because the voltage drop occurred over a larger distance. The vertical field was reduced from 1.25times106V/cm to 6.9times105V/cm when the oxide thickness was increased from 11.7 to 21.6 nm.