研究论文
A CMOS 6-Bit 16-GS/s time-interleaved ADC with digital background calibration
Chun-Cheng Huang, Chung‐Yi Wang, Jieh-Tsorng Wu
National Yang Ming Chiao Tung University
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摘要与影响
摘要 · 完整
An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.
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学术脉络
学科主题
工程Analog and Mixed-Signal Circuit Design
CCD and CMOS Imaging Sensors · Sensor Technology and Measurement Systems
参考文献 3
A background comparator calibration technique for flash analog-to-digital converters
被引 47Chun-Cheng Huang, Jieh-Tsorng Wu · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2005
A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection
被引 37Chung‐Yi Wang, Jieh-Tsorng Wu · IEEE Transactions on Circuits and Systems I Regular Papers · 2008
A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process
被引 227Geert Van der Plas, S. Decoutere, S. Donnay · 2006
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引用本文 24
A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration
被引 261Manar El-Chammas, Boris Murmann · IEEE Journal of Solid-State Circuits · 2011
A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration
被引 226Wenbo Liu, Pingli Huang, Yun Chiu · IEEE Journal of Solid-State Circuits · 2011
A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques
被引 127Chun-Cheng Huang, Chung‐Yi Wang, Jieh-Tsorng Wu · IEEE Journal of Solid-State Circuits · 2011
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