First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects

In this work, for the first time, the Flip FET (FFET), a novel stacked transistor technology with self-aligned active and interconnects on both sides of wafer, is proposed and experimentally demonstrated. Two layers of transistors are formed on the same active and back-to-back stacked, featuring a much more manufacturing-friendly process flow with lower aspect ratio (AR) than CFET. Standard cell (STC) libraries with minimum 2.5 track height (2.5T) design are established, proving further scaling possibility and better routability over CFET. Benefited from the dual-side process, FFET also has better design flexibility with no restriction on N/P polarity for each transistor layer, enabling a bipolar SRAM with further 12% area reduction over CFET SRAM and at least 35.9% over FinFET SRAM, respectively. Meanwhile, based on fins, FFET outperforms CFET with 21.5% higher frequency at iso-power and 45.0% lower power at iso-frequency. Furthermore, for nanosheet-based ones, FFET shows extra benefits over CFET with larger nanosheet width (WNS), with 14.5% higher frequency at iso-power at the same footprint. New concepts of dual-side interconnects are introduced and the P&R result of a RISCV321 core further validates the superiority of FFET with more than 31.3% area reduction compared with CFET.