Package Modeling and Analysis for Heterogeneous Integration

Advanced semiconductor packaging is now used by semiconductors companies to meet both cost and performance requirements (e.g. bandwidth, latency, power, etc.) for artificial intelligence (AI) applications using heterogeneous multi-chiplet architectures. These packaging techniques include flip-chip, wafer-level packaging (both fan-in and fan-out) and 3D-Heterogeneous Integration (3D-HI) using package-on-package and hybrid/direct bonding. As detailed in several packaging roadmaps, chip-package-board co-design supported by multi-physics modeling and analysis are key underpinning technologies to support heterogeneous architectures that combine multi-chiplets within a single package.