Device-Circuit Co-Design Investigation of a Structurally Engineered 7 nm InGaAs-SOI Complementary FinFET for Wide-Temperature CMOS Operation

In this work, we report a structurally optimized design of 7 nm InGaAs-SOI complementary FinFET, and demonstrate thermal reliability of InGaAs-based logic device and circuit-level behavior over a wide temperature range of ∼ 200– ∼ 700 K. The proposed 7 nm InGaAs–SOI FinFET with optimized fin architecture achieves Vth values of 0.50 and 0.60 V for the n-type and p-type FinFETs, respectively, with an exceptional ON/OFF current ratio of 6.21 × 10 10 , subthreshold swing (SS) of 67.44 mV dec − 1 , and drain-induced barrier lowering (DIBL) of 59.20 mV V − 1 . It is observed that the InGaAs–SOI FinFET device exhibits strong self-heating characteristics and superior short-channel immunity at elevated operating temperatures compared to conventional Si CMOS FinFETs and wide-bandgap technologies such as SiC. Furthermore, to mitigate the inherent imbalance at the circuit level, an asymmetric complementary inverter is designed using a 4:1 pMOS-to-nMOS Fin ratio to offset the electron–hole mobility disparity. The optimized binary inverter sustains reliable switching operation and exhibits improved voltage gain with maintaining positive noise margins up to 700 K at a low supply voltage of 1.5 V. These findings highlight the promise of InGaAs-SOI CMOS FinFETs for high-speed logic applications operating in elevated-temperature environments, such as defense and space systems.