Automatic generation of VHDL code for a railway interlocking system
Martín Nicolás Menéndez, Santiago Germino, Facundo Santiago Larosa, Ariel Lutenberg
Consejo Nacional de Investigaciones Científicas y Técnicas Universidad de Buenos Aires National Technological University
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摘要与影响
This article introduces a novel technique to automatically analyse a railway network geographical representation and produce a suitable FPGA railway interlocking system by generating its VHDL hardware description. This approach accelerates the design, implementation and testing phases on different topologies. We review the automated tools developed - which are part of a comprehensive workflow - and present the results for topologies of varying complexities.
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计算机 / AIEmbedded Systems Design Techniques
Embedded Systems and FPGA Applications · VLSI and FPGA Design Techniques