PLC implementation in the form of a System-on-a-Chip

The aim of the paper is to present the implementation of a PLC designed in the form of a System-on-a-Chip. The presented PLC is compatible with the IEC61131‒3 standard. More precisely, the Instruction List language is the native language of the designed CPU, so there is no need for multiple language transformations. In the proposed solution each instruction of the CPU program written in Instruction List is directly translated to machine code. The designed CPU is capable of performing logic operations up to 32-bit Boolean data types. However, the developed CPU is very flexible due to its architecture: data memory can be addressed as bit/byte/word/dword. Moreover, diverse blocks such as timers, counters, and hardware acceleration blocks, can be connected to the CPU by means of an APB AMBA bus. The designed PLC has been implemented in an FPGA device and can be used in cyber-physical systems and Industry 4.0.