Design and Implementation of a Broadband Radar Receiver Frequency Source for 3.5 GHz Fixed Intermediate Frequency

Along with the development of intelligent algorithms in radio frequency systems, the design of frequency source is gradually becoming more accurate, adaptable, and intelligent. In order to meet the needs of a wide band radar receiver for a fixed 3.5 GHz IF, a high performance frequency source design method is proposed, which combines the Phase-Locked Loop (PLL) and the Direct Digital Synthesis (DDS) architecture. In this paper, a Backpropagation (BP) Neural Network and Long Short-Term Memory (LSTM) are used to model the temperature drift and adaptive compensation. Phase noise and power fluctuation are efficiently supplied by implementing a closed loop reconstruction and feedback adjustment mechanism in an Field-Programmable Gate Array (FPGA) control platform. Experimental results show that the frequency source maintains a maximum frequency deviation of ± 13.4 Hz in the range of 25 °C to 45 °C, achieves a phase noise of better than -95 dBc/Hz at 1 kilohertz( kHz), and shows a power stability fluctuation of less than 0.35 dBm during 24 hour operation. These properties meet the dynamic and spectral purity requirements of 12-bit ADCs.This research verifies the robustness and engineering feasibility of the RF design in high dynamic environment.