FPGA Implementation of a Real-Time Edge Detection System Based on an Improved Canny Algorithm

Canny edge detection is one of the most widely used edge detection algorithms due to its superior performance. However, it is complex, time-consuming process and has a high hardware cost. In addition, most of the existing implementations of the algorithm use the same fixed pair of high and low threshold values for all input images. This cannot automatically adapt to changes in the external detection environment and results in decreased performance. To overcome these issues, an improved Canny algorithm is proposed in this paper. It uses the Sobel operator and approximation methods to calculate the gradient magnitude and direction for replacing complex operations with reduced hardware cost. Otsu’s algorithm is introduced to adaptively determine the image threshold. However, Otsu’s algorithm has division operations,and the division operation is complex, has low efficiency and slow speed. We introduce a logarithmic unit to turn division into a subtraction operation that is easy to implement by hardware but which does not affect the selection of the threshold. Experimental results show that the system can detect the edge of the image well without adjusting the threshold value when the external environment changes and requires only 1.231 ms to detect the edges of the 512 x 512 image when clocked at 50 MHz. Compared with existing FPGA implementations, our implementation uses the least amount of logical resources. Thus, it is more suitable for platforms have limited logical resources.