A Staged-Information Framework for Cross-Design Routing Architecture Recommendation in Embedded FPGAs

Selecting a routing architecture for Embedded FPGAs (eFPGAs) is expensive because candidate quality normally becomes available only after physical implementation. We formulate this task as a decision across information stages under a verification budget of five candidates and compare information obtained from prior evaluations, placement, and early routing. Across 52 circuits from five application domains, history-only H0 achieves 82.69% coverage when retaining five candidates under a 3% area-delay product tolerance without implementing any target candidate. Placement information at P0 reaches 82.05% and provides no confirmed improvement. RT1 incorporates the routing state recorded at the first PathFinder iteration and raises coverage to 96.15%, a confirmed gain of 14.10 percentage points over P0. A matched ScalarOnly ablation shows that both model representations benefit from this response, while StageRank retains the exact optimum more often at RT1. Together, these results demonstrate that the proposed framework combines reusable historical knowledge, graph representations, and early physical observations to support systematic and efficient eFPGA architecture exploration. Historical evaluations provide a strong basis for initial selection across circuits, while information from the target circuit adds confirmed value only after the interaction between circuit and architecture becomes observable. RT1 is the earliest stage evaluated to provide this information and is therefore selected as the fixed stage under the evaluated protocol.