A Weighted NBTI/HCD Coupling Model in Full VG/VD Bias Space with Applications to SRAM Aging Simulation

In this paper, a coupled negative bias temperature instability (NBTI)/hot carrier degradation (HCD) failure model is proposed on the 2-D voltage plane for aging simulation of SRAM circuits. According to the physical mechanism of failure, based on the reaction–diffusion and hot carrier energy-driven theory, revised degradation models of threshold voltage shift (∆Vth) for the NBTI and HCD are established, respectively, with explicit expressions for gate voltage (VG)/drain voltage (VD). An NBTI/HCD coupling model is built on the 2-D {VG, VD} voltage plane with a weighting factor in the form of VG and VD power law. The model also takes into account the AC effect and long-term saturation behavior. The predicted ∆Vth under various stress conditions shows an average relative error of 11.6% with experimental data across the entire bias space. SRAM circuit simulation shows that the read static noise margin (RSNM) and write static noise margin (WSNM) have a maximum absolute error of 4.2% and 3.1%, respectively. This research provides a valuable reference for the reliability simulation of nanoscale integrated circuits.