VTH-Adjustable p-Channel GaN Field-Effect Transistor with an Inserted n-GaN Layer

In this work, a novel Schottky-gated p-channel GaN field-effect transistor (PFET) with a tunable n-GaN sub-gate layer is investigated. Terminal-current analysis under the actual drain-bias condition shows that the gate-current contribution remains limited within the defined effective operating range of VGS ≥ −3.2 V, whereas gate-related current becomes significant at more negative gate biases. Carrier-resolved and spatial current analyses further confirm that, within this operating range, the drain current is predominantly carried by holes through an interfacial hole channel near the p-GaN/AlGaN heterointerface. Benefiting from the intentionally introduced p–n junction beneath the groove gate, the built-in electric field effectively depletes the p-GaN channel, enabling a robust transition from depletion-mode to enhancement-mode (E-mode) operation. By precisely scaling the n-GaN layer thickness (0–5 nm) and donor concentration (3.0 × 1017 cm−3 to 3.0 × 1019 cm−3), the buried p-n junction modulates the depletion condition and hole distribution beneath the gate. The optimized device exhibits a significantly improved subthreshold swing (SS) of 348 mV/dec, while maintaining a stable ION/IOFF ratio on the order of 102. This tunable sub-gate architecture provides a highly flexible platform for optimizing E-mode GaN PFETs, showing great promise for high-performance complementary logic applications.